1. Field of the Invention
The present invention relates to a method for programming a memory device suitable to minimize the lateral coupling effects between memory cells.
More specifically, the invention relates to a method for programming a memory device of the type comprising at least one memory cell matrix, the method comprising the steps of:                erasing of said memory cells;        soft programming of said memory cells; and        complete programming of a group of said memory cells, each of them storing its own logic value.        
The invention also relates to a memory device suitable to implement the proposed method.
The invention particularly, but not exclusively, relates to a memory device of the Flash type and the following description is made with reference to this field of application for convenience of explanation only.
2. Description of the Related Art
As it is well known, the continuous decrease (the so called shrinking) of integrated device sizes in modern technologies brings about several problems.
In particular, in the case of memory devices, the more and more reduced distances between memory cells makes the electrical interactions between adjacent cells in the usual cell matrix structures stronger and stronger.
It is in fact to be remembered that the elements of a Flash memory device are substantially floating gate memory cells, realized on a semiconductor substrate 1 wherein a source region 2 and a drain region 3 are defined as well as a body region 4 interposed between the source 2 and the drain 3 region, the substrate 1 being overlapped by a first dielectric layer 5, so called gate dielectric, by a first polysilicon layer, known as poly1 and defining the floating gate 6, by a second dielectric layer 7, so called dielectric interpoly, and by a second polysilicon layer, known as poly2 and defining the control gate 8, as schematically shown in FIG. 1, which represents a floating gate memory cell, globally and schematically indicated with 10.
The integrated structure of the memory cell 10 has different capacitive couplings due to the alternation of conductive and insulating layers, and in particular the following capacitances are defined:
CGS: between the floating gate 6 and the source region 2;
CGD: between the floating gate 6 and the drain region 3;
CGB: between the floating gate 6 and the body region 4; and
CI: between the polysilicon layers defining the floating gate 6 and the control gate 8.
Such capacitive couplings also involve the cell matrix as a whole, where there is a same alternation of dielectric/conductive layers and in particular it results to be relevant between the floating gates of consecutive cells inside the matrix.
It has been however verified that, for the technologies being currently available at 0.15 μm, the capacitive coupling between the floating gates of adjacent cells can be considered negligible. In this case, it is possible to model each memory cell in its electrical behavior as independent from the adjacent cells.
In reality, for the currently developing technologies, and, all the more reason, for future ones, such capacitive interaction between adjacent cells is no more negligible and therefore it is to be considered in the correct description of the cell electric behavior.
FIG. 2 shows, by way of example, a matrix 20 of memory cells 10, organized in a known way in rows, or wordlines WL, and columns, or bitlines BL, also indicating the possible capacitive lateral couplings Cx, Cy and Cxy which establish between floating gates 6 of adjacent cells.
The mutual capacitive coupling between adjacent memory cells particularly implies an alteration of the threshold value of a cell under examination, when the threshold values of adjacent cells vary, i.e. when their operative conditions vary.
In particular, such mutual coupling can be represented by means of the following relation:αacc=(2Cx+2Cxy+Cy)/Ctot;
αacc being a multiplicative constant which takes into account the coupling between adjacent cells;
Cx, Cxy and Cy being the values of the parasite capacitances due to the lateral couplings of adjacent cells; and
Ctot being the global value of the capacitances connected to the floating gate of a cell.
With the decrease of the integration geometries and thus of the distances between adjacent cells, the ratio between the lateral parasite capacitances Cx, Cxy and Cy and the total capacitance Ctot increases: the threshold value of a cell thus becomes a function also of adjacent cell thresholds.
In particular, during the programming step of the memory matrix, the floating gates of the cells being programmed are brought to a low potential value.
Taking into consideration a given cell there occurs that, due to the above-described capacitive coupling, such potential value is at least partially transferred to its floating gate from the floating gates of adjacent cells being programmed.
This alteration of the floating gate potential turns out as an increase of the threshold value of the cell under test, even in the case wherein the neat charge of its floating gate has not been changed and thus its status has not been changed, i.e. of the value stored therein between the possible logic values.
This phenomenon is even more marked in the case of Flash memory devices, in which all the cells of a sector are erased all together and then selectively programmed. In particular, it should be noted that the threshold increase effect also involves cells having been already correctly programmed which are however adjacent to a cell being programmed.
For two-level or single bit memory devices, such threshold increase during the programming step is not problematic if the “disturbed” cells store logic “0” values. Vice versa this interaction can be dangerous if the “disturbed” cells store logic “1” values, corresponding to a low threshold value, since the threshold margin, suitably designed for a correct reading of the memory device during its life, is reduced.
Moreover, for multilevel memory devices, the above-indicated problems for two-level memory devices, are worsened since, besides the case of the low threshold level or minimum level, also in the case of possible intermediate levels a shift of the cell threshold values can lead to reading errors of the memory device itself.
For maintaining the threshold margins unaltered between the distributions of the various levels and the corresponding reading references usually used for reading the memory device it is consequently necessary to increase the separation in terms of threshold values between the references relative to the possible programmed levels of an amount equal to the maximum disturb a cell can have, and thus to widen the so-called threshold window. In substance, the parasitic widening of the threshold distribution due to the interaction between adjacent cells is to be taken into account.
All this leads however to have a reduced reliability due to the general increase of the electrical fields in retention, as schematically shown in FIGS. 3A and 3B where the distributions of the threshold values are shown for different levels of a multilevel device, in particular able to store two bits for memory cell, in the case of standard positioning of the references (FIG. 3A) and with the references positioned considering the distribution widening caused by the lateral couplings (FIG. 3B).
In particular, such figures indicate with:
DV the voltage reference of the so called depletion verify;
EV the erasing verify voltage reference;
R1 a first reading voltage reference;
PV1 the programming verify voltage reference of a first programmed level;
R2 a second reading voltage reference;
PV2 the programming verify voltage reference of a second programmed level;
R3 a third reading voltage reference; and
PV3 the programming verify voltage reference of a third programmed level.
In particular, by comparing FIG. 3A and FIG. 3B it is immediate to verify how each threshold distribution of the considered levels widens, an effect of the lateral parasitic couplings between adjacent cells, of a maximum level ΔVT,acc equal to:ΔVT,acc=αaccΔVTcells—lateral;
wherein
ΔVT,acc is the maximum threshold voltage variation of a cell under examination;
αacc is the coupling multiplicative constant; and
ΔVTcells—lateral is the threshold voltage variation of the cells being adjacent to the cell under test, further to the programming thereof.
Such shift of the threshold distributions makes the use of different positions of the voltage references for reading the different levels necessary, with a total shift (the shift of the last considered level) equal to 3ΔVT,acc.
Particular integration technologies are also known able to reduce such shifts of the threshold levels by minimizing the capacitive couplings between adjacent cells obtained by modifying the method for integrating the cells themselves. The memory devices thus obtained have therefore reduced values of the capacitive couplings between adjacent cells which reduce, but do not eliminate, the phenomenon of the threshold level variations, these latter continuing however to limit the use of the memory devices thus obtained, in particular in case of multilevel applications.